ASIC Design Engineer - Backend

Photeon Technologies GmbH

Employment Type: full time
Minimum Training: HTL-Matura
Language: English
Location: Dornbirn
Contact Person: Johanna Ammann

Applications please by E-mail

Job description

Are you interested in new technologies and future-oriented projects in the field of chip design? Then Photeon is the right choice! To strengthen our international team, we are looking for talents in chip development in the field of "digital chip design".

Field of activity:

  • Full RTL2GDS flow
  • DFT
  • ATPG
  • Synthesis
  • Place&Route
  • Static Timing Analysis
  • Logical Equivalence Check
  • Physical verification (DRC/LVS)


Requirements profile:

  • Higher technical education (e.g. university, technical college) in the field of electronics, mechatronics, computer science, technical physics or similar
  • Knowledge of Linux operating system is an advantage
  • Good written and spoken English language skill
  • Familiarity with Cadence and Synopsys tools
  • Support backend ASIC design from logic synthesis to timing closure
  • Implement scan ATPG and achieve high test coverage
  • Work with front end design team and physical design team to support timing and functional ECOs

More Information

What we offer:

  • Exciting, varied work in a growing and internationally active company
  • Good familiarization and ongoing support
  • Helpful colleagues
  • Flexible working time
  • Modern office space
  • Regular employee evaluation and career planning
  • Team building events
  • Regular trainings (internal and external)
  • Support in relocation
  • Competitive compensation package (minium salary according to collective agreement - ST1, Regelstufe gross/year EUR 43.316; ST2, Regelstufe gross/year EUR 50.652 - actual salary will be above these numbers)


Johanna Ammann
Hintere Achmühlerstraße 1
6850 Dornbirn


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